Do you know how a chip is designed? Do you know how the designed chip is produced? After reading this article you have a general understanding. 1 complex and cumbersome chip design process The process of chip manufacturing is like building a house with Lego. After first wafers are used as foundations, and then the stacking process of chips is stacked up, the necessary IC chips can be produced (these will be described later). However, without a blueprint, it is useless to have a strong manufacturing capability. Therefore, the role of the architect is very important. But who exactly is the architect in IC design? This article next describes IC design. In the IC production process, ICs are mostly planned and designed by professional IC design companies, such as MediaTek, Qualcomm, Intel, and other famous manufacturers. They all design their own IC chips and provide chips of different specifications and performance to select downstream manufacturers. Because ICs are designed by each company, IC design relies on engineers' skills. The quality of engineers affects the value of a company. However, what steps do engineers have when designing an IC chip? The design process can be simply divided into the following. Designing the first step and setting goals The most important step in IC design is specification. This step is like deciding on a few rooms and bathrooms before designing a building. There are building regulations that need to be followed, and the design is done after all the functions have been determined so that no additional time is needed for subsequent modifications. The IC design also needs to go through similar steps to ensure that the designed chip will not have any errors. The first step in specification development is to determine the purpose and effectiveness of the IC and set the general direction. The next step is to see which protocols are to be complied with. A chip like a wireless network card needs to comply with IEEE 802.11 or other specifications. Otherwise, the chip will not be compatible with the products on the market, making it impossible to connect with other devices. The last step is to establish the implementation method of this IC, allocate different functions into different units, and establish methods for linking different units, so that the specification is completed. After designing the specifications, the design details of the chip are then followed. This step is like taking a preliminary note of the building's plan and depicting the overall outline to facilitate subsequent drawing. In an IC chip, a circuit is described using a hardware description language (HDL). Frequently used HDLs include Verilog, VHDL, and the like, and an IC function can be easily expressed by a code. The next step is to check the correctness of the program's functionality and continue to modify it until it meets the desired functionality. ▲ Verilog Example of 32 bits Adder With computers, everything becomes easy With the complete plan, the next step is to draw a blueprint for the design. In IC design, the logic synthesis step is to put the HDL code that is determined to be correct, into the electronic design automation tool (EDA tool), and let the computer convert the HDL code into logic circuit to generate the following circuit diagram. After that, it is determined repeatedly whether the logic gate design conforms to the specifications and changes until the function is correct. ▲ Result of the synthesis of the control unit Finally, the synthesized code is put into another set of EDA tool for circuit layout and placement (Place And Route). After continuous testing, the following circuit diagram will be formed. Different colors such as blue, red, green and yellow can be seen in the figure, and each different color represents a mask. As for how to use the mask? ▲ Commonly used calculation chip - FFT chip, complete circuit layout and winding results Layer masks, stacking a chip First of all, it is known that an IC generates multiple masks. These masks have upper and lower layers, and each layer has its own task. The following figure shows a simple photomask example, taking the most basic component CMOS in an integrated circuit as an example. CMOS is called Complementary metal-oxide-semiconductor (NMOS and PMOS). Combine to form CMOS. What is a metal oxide semiconductor (MOS)? This kind of device that is widely used in the chip is more difficult to explain, and the average reader is also more difficult to figure out. There is no more detailed study here. In the figure below, the left side is the circuit diagram after circuit layout and winding. It is known in the front that each color represents a mask. On the right is how each photo mask spreads out. The production process starts with the bottom layer and follows the method mentioned in the previous IC chip manufacturing process. It is produced layer by layer, and finally the desired chip will be produced. At this point, there should be a preliminary understanding of IC design. As a whole, it is clear that IC design is a very complicated profession. Thanks to the maturity of computer-assisted software, IC design can be accelerated. The IC design factory relied heavily on the wisdom of the engineers. Each step described here has its own specific knowledge. Each of these steps can be independently developed into multiple professional courses. For example, writing a hardware description language is not purely a matter of knowing the programming language. You also need to understand how logic circuits work, how to convert the required algorithms into programs, and how the synthesis software converts programs into logic gates. Among the major semiconductor design companies are Intel, Qualcomm, Broadcom, Infinity, Merck, Xilinx, Altera, MediaTek, Hass, Spreadtrum, ZTE Microelectronics, Huada, Datang, Zhixin, Duntai, Silan, and China Star. , etc. 2 What is a wafer? In semiconductor news, there are always mentions of wafer factories that are marked with dimensions, such as 8-inch or 12-inch fabs. However, what is the so-called wafer in the end? Which part of the 8 inch refers to? What is the difficulty in producing large-size wafers? The following is a step-by-step introduction to the most important foundation of semiconductors - what exactly is a "wafer." Wafers are the foundation for making all kinds of computer chips. We can compare chip manufacturing to building houses with Lego bricks, stacking layers one by one to complete our own desired style (ie, various types of chips). However, if there is no good foundation, the covered house will squat around. It is not what you want. In order to make a perfect house, you need a stable base plate. For chip manufacturing, this substrate is the wafer that will be described next. (Souse: Flickr/Jonathan Stewart CC BY 2.0) First of all, first recall that when a child was a Lego building block, the surface of the building blocks would have a small round projection. With this construction, we could stack the two building blocks stably without using glue. . Chip fabrication also fixes the subsequently added atoms and substrates together in a similar manner. Therefore, we need to find a substrate with a neat surface to meet the requirements for subsequent manufacturing. In solid materials, there is a special crystal structure - Monocrystalline. It has the characteristics of atoms arranged one after the other, forming a flat surface of the atom. Therefore, the use of single crystal wafers can meet the above needs. However, there are two main steps in how to produce such a material, namely purification and pulling, and then the material can be completed. How to make a single crystal wafer The purification is divided into two stages. The first step is the metallurgical grade purification. This process is mainly to add carbon to convert silicon oxide into silicon with a purity of more than 98% in the form of redox. Most of the metals extracted, such as iron or copper, are obtained in such a way that they are of sufficient purity. However, 98% is still not enough for chip manufacturing and still needs further improvement. Therefore, Siemens process will be further used for purification. In this way, high-purity polysilicon required for semiconductor process will be obtained. ▲ Silicon Column Manufacturing Process (Source: Wikipedia) Then, it is the step of pulling crystals. First, the high purity polysilicon previously obtained is melted to form liquid silicon. After that, the single-crystal silicon seed is brought into contact with the surface of the liquid and slowly pulled up while rotating. As to why single-crystal silicon is needed, because the arrangement of silicon atoms is the same as that of people, they will need to be ranked first so that the right people can arrange them correctly. Silicon is the important leader, and later atoms know how to line up. Finally, after the silicon atoms leaving the liquid surface solidify, the aligned single crystal silicon column is completed. ▲ monocrystalline silicon column (Souse: Wikipedia) However, what does 8 inch and 12 inch represent? He refers to the crystal column that we produce, the part that looks like a pencil shaft, the diameter of the surface that has been processed and cut into thin circular plates. As for the difficulty of manufacturing large-size wafers? As mentioned earlier, the manufacturing process of the crystal column is like forming marshmallows, and it is molded while rotating. If you have made marshmallows, you should all know that it is very difficult to make big and solid marshmallows, and the same is true for pulling crystals. The speed of pulling and the temperature control will affect the quality of the crystal columns. Therefore, the larger the size, the higher the speed and temperature requirements of pulling the crystals. Therefore, it is more difficult to make high-quality 12-inch wafers than 8-inch wafers. However, an entire silicon pillar cannot be made into a chip-manufactured substrate. In order to produce a single silicon wafer, a silicon knife is then required to cut the silicon crystal pillar laterally into a wafer. The wafer can then be formed by polishing. Make the required silicon wafers. After so many steps, the manufacturing of the chip substrate is completed, and the next step is the step of stacking the house, that is, the chip manufacturing. As for how to make a chip? 3-layer stacked chip After describing what silicon wafers are, it is also known that manufacturing IC chips is like building a house with Lego bricks, creating layers of layers that create the shapes that they desire. However, there are quite a few steps to building a house. IC manufacturing is the same. What steps are there to make an IC? This article will introduce the IC chip manufacturing process. Before we begin, we must first understand what the IC chip is. The IC, the full name Integrated Circuit, is known by its name as a circuit that is designed to be assembled in a stacked manner. With this method, we can reduce the area required to connect the circuit. The following figure shows the 3D map of the IC circuit. It can be seen from the figure that its structure is like the beams and columns of the house, stacked one on top of the other, which is why the IC manufacturing is like building a house. ▲ 3D profile of the IC chip. (Source: Wikipedia) From the 3D cross-sectional view of the IC chip in the above figure, the dark blue part at the bottom is the wafer introduced in the previous chapter. From this figure, it can be more clearly known how important the wafer substrate plays a role in the chip. As for the red and khaki-colored parts, it is the place to be completed at the time of IC production. First of all, the red part can be compared here to the first floor lobby in a tall building. The lobby on the first floor is the gateway to a house. It is accessed here and there is usually more functionality under the control of traffic. Therefore, when compared with other floors, it will be more complex and require more steps. In the IC circuit, this hall is the logic gate layer, which is the most important part of the entire IC. By combining multiple logic gates together, a fully-functional IC chip is completed. The yellow part is like an ordinary floor. Compared with the first floor, there will be no complicated structures, and there will not be much change in each floor when it is built. The purpose of this layer is to connect the logic gates of the red part. The reason why so many layers are needed is because there are too many lines that need to be linked together. In a single layer that can't accommodate all the lines, we have to stack several layers to achieve this goal. Among these, the lines of different layers are connected up and down to meet the wiring requirements. Layered construction, layer by layer architecture After knowing the structure of the IC, the next step is to describe how to make it. Imagine if we want to do a fine picture with a paint sprayer, we need to cut out the graphic cover and cover it on paper. Then spray the paint evenly on the paper. After the paint is dry, remove the mask again. Repeatedly repeating this step will complete the neat and complex graphics. Manufacturing ICs is stacked in a similar manner, layer by layer, by means of masking. When making an IC, you can simply divide the above 4 steps. Although the actual manufacturing process differs in the manufacturing steps and the materials used are different, generally similar principles are used. This process is a little different from paint painting. The IC is made of paint and then covered. Paint painting is to cover and paint. The following describes the various processes. Finally, many IC chips will be completed on a whole wafer. As long as the finished square IC chips are cut off, they can be sent to the packaging factory for packaging. What is the packaging factory? It will be followed by instructions. ▲ Comparison of wafers of various sizes. (Source: Wikipedia) Among them, the main foundries are Groovy, Samsung Electronics, Tower Jazz, Dongbu, Magna, IBM, Fujitsu, Intel, Hynix, TSMC, UMC, SMIC, Powerchip, Hua Hong, De Mao Wuhan Xinxin, Huawei, Huali, Lixin. 4 nanometer process is what? Samsung and Taiwan Semiconductor Manufacturing Co., Ltd. are playing very hot on advanced semiconductor manufacturing processes. They both want to grab an opportunity to win orders in the wafer foundry, almost becoming a battle between 14nm and 16nm, but 14nm and 16nm respectively. What is the meaning of the number and what part is it referring to? What benefits and problems will it bring in the future after narrowing the process? In the following, we will give a brief explanation of the nanometer process. How fine is nano? Before you begin, understand what nanotechnology really means . In mathematics, the nanometer is 0.000000001 meters, but this is a rather poor example. After all, we only see that there are many zeros after the decimal point, but there is no actual feeling. If you compare the thickness of nails, it may be more obvious. Actual measurement with a ruler shows that the thickness of the nail is about 0.0001 m (0.1 mm), which means trying to cut the side of a nail into 100,000 lines, each line is equivalent to about 1 nanometer. This can be slightly imagined how tiny 1 nanometer is. After knowing how small the nanometers are, we must also understand the intention of narrowing down the process. The main purpose of reducing the size of transistors is to insert more transistors into smaller chips so that the chips will not become more technologically advanced. Large; second, can increase the processor's computing efficiency; Moreover, reducing the size can also reduce power consumption; Finally, after the chip size is reduced, it is easier to stuff into the mobile device to meet the future needs of thin and light. Looking back at what is the nanometer process, taking 14nm as an example, the manufacturing process means that in the chip, the minimum line size can be 14nm, and the figure below shows the longitude of the conventional transistor, as an example. The main purpose of reducing the transistor is to reduce the power consumption. However, which part should be reduced to achieve this goal? The L in the lower left figure is the part we want to shrink. By reducing the gate length, the current can be routed from the Drain side to the Source side in a shorter path (if you are interested, you can use Google's MOSFET search, which will be explained in more detail). In addition, the computer operates on 0 and 1. How do you use a transistor to meet this goal? The practice is to determine whether the transistor has current flow. When the voltage is supplied to the Gate (green box), the current will flow from the Drain terminal to the Source terminal. If no voltage is supplied, the current will not flow, so that 1 and 0 can be represented. (As to why you should use 0 and 1 for judgment, if you are interested, you can go to Chablin algebra. We use this method to make a computer.) Size reduction has its physical limitations However, the process cannot be infinitely reduced. When we shrink the transistor to about 20 nanometers, we will encounter problems in quantum physics, which will cause the transistor to leak electricity, which will offset the benefits obtained by reducing the L value. As an improvement, the concept of FinFET (Tri-Gate) is introduced, as shown in the top right figure. In Intel's previous explanations, it can be seen that by introducing this technology, leakage due to physical phenomena can be reduced. More importantly, this method can increase the contact area between the Gate and the lower layer. In traditional practice (above left), the contact surface has only one plane, but after using the FinFET (Tri-Gate) technology, the contact surface will become three-dimensional, and the contact area can be easily increased so that the same contact can be maintained. Making the Source-Drain side smaller under the area has a lot of help in reducing the size. Finally, why is anyone saying that major plants will face considerable challenges when they enter the 10-nanometer process, mainly because the size of one atom is about 0.1 nanometers, and in the case of 10 nanometers, one line has less than 100 atoms, It is very difficult to produce, and if there is an atomic defect, such as an atom falling out or impurities in the process, it will produce an unknown phenomenon, affecting the yield of the product. If you can't imagine this difficulty, you can do a little experiment. Form a 10×10 square with 100 beads on the table, and cut a piece of paper to cover the beads. Then use a small brush to brush off the next bead. Finally make him a 10×5 rectangle. In this way, we can know the difficulties faced by major plants and how difficult it is to achieve this goal. As Samsung and Taiwan Semiconductor Manufacturing Co. Ltd. will complete mass production of 14nm and 16nm FinFETs in the near future, both want to compete for Apple's next-generation iPhone chip foundry. We will see great business competition, and we will also get more power savings. , thin mobile phones, thanks to the benefits brought by Moore's Law. 5 tell you what is the package After a long process, from design to manufacturing, an IC chip was finally obtained. However, a chip is quite small and thin. If it is not protected, it will be easily scratched and damaged. In addition, because of the tiny size of the chip, it would not be easy to manually place on a circuit board without using a larger size housing. Therefore, this article next describes the package description. At present, there are two kinds of common packaging, one is common in the electric toy, black looks like a dip in the DIP package, and the other is a common BGA package when buying a boxed CPU. As for other packaging methods, there are PGA (Pin Grid Array; Pin Grid Array) of the earlier CPU or improved QFP (Plastic Quad Flat Packing) of DIP. Because there are too many packaging methods, the following will introduce the DIP and BGA packages. Traditional packaging, enduring The first thing to introduce is the Dual Inline Package (DIP). From the figure below, you can see that the IC chip with this package looks like a black bar under the double row of pins, which is very impressive. The packaging method is the earliest IC packaging technology and has the advantage of low cost. It is suitable for small chips that do not require too many wires. However, because most plastics are used, the heat dissipation effect is poor and cannot meet the requirements of current high-speed chips. Therefore, most of the chips that use this package are enduring chips, such as the OP741 in the figure below, or IC chips that are not required for the operation speed and have smaller chips and fewer contacts. ▲ The IC chip on the left is the OP741, which is a common voltage amplifier. The figure on the right shows its sectional view. This package connects the chip to the metal lead frame with a gold wire. (Source: Wikipedia on the left and Wikipedia on the right) As for the Ball Grid Array (BGA) package, the package is smaller in size than the DIP and can be easily placed into a smaller device. In addition, because the pin is located below the chip, it can accommodate more metal pins than the DIP It is suitable for chips that require more contacts. However, the use of such a packaging method has a high cost and a complicated connection method, and is therefore mostly used in high-priced products. ▲ The left figure shows the chip in BGA package. The figure on the right shows a BGA schematic using a flip-chip package. (Source: Wikipedia, left) The rise of mobile devices, new technologies are on the stage However, using these packaging methods can consume a considerable amount of volume. The current mobile devices, wearable devices, etc., require a considerable number of components. If the individual components are individually packaged and combined, it will consume a very large space. Therefore, there are currently two methods that can meet the requirements for downsizing, namely SoC ( System On Chip) and SiP (System In Packet). When the smart phone first emerged, the term SoC was found in major financial magazines. But what exactly is SoC? In simple terms, ICs with different functions are integrated into one chip. With this method, not only can the size be reduced, but also the distance between different ICs can be reduced and the chip's calculation speed can be increased. As for the production method, it is during the IC design stage that various ICs are put together and then a mask is created through the previously described design process. However, SoCs are not just an advantage. Designing a SoC requires considerable technical cooperation. When the IC chips are individually packaged, there is external protection of each package, and the distance between the IC and the IC is relatively long, and relatively no interference may occur. However, when all ICs are packaged together, it is the beginning of a nightmare. The IC design plant will change from the original simple design of the IC to an IC that understands and integrates each function and increases the workload of the engineer. In addition, there are many situations in which high-frequency signals such as communication chips may affect other functions such as ICs. In addition, the SoC also needs to obtain the IP (intellectual property) authorization from other vendors in order to put components designed by others into the SoC. Because the production of the SoC requires the design details of the entire IC, a complete mask can be made, which also increases the design cost of the SoC. Some people may question why not design one yourself? Because designing various kinds of ICs requires a lot of knowledge related to the IC, only companies like Apple that have a lot of money have the budget to be able to excavate top engineers from well-known companies to design a brand-new IC. More research and development cost-effective. Eclectic solution, SiP appeared As an alternative, SiP jumped to the stage of integrating chips. Unlike SoCs, it is the purchase of ICs from various companies. The ICs are packaged for the last time. This reduces IP authorization and significantly reduces design costs. In addition, because they are separate ICs, the degree of interference with each other has dropped significantly. ▲ Apple Watch uses SiP technology to encapsulate the entire computer architecture into a single chip, not only meeting the desired performance but also shrinking the size, allowing the watch to have more room to put the battery. (Source:Apple's official website) Products using SiP technology are the best-known non-Apple Watch. Because the internal space of Watch is too small, it cannot adopt the traditional technology, SoC design cost is too high, SiP becomes the first choice. With SiP technology, not only can the size be reduced, but the distance between ICs can also be narrowed to become a feasible compromise solution. The following figure shows the structure of the Apple Watch chip. It can be seen that quite a few ICs are included. ▲ The SiP packaged S1 chip internal configuration diagram is used in the Apple Watch. (Source:chipworks) After the package is completed, it is time to enter the test phase. At this stage, it is necessary to confirm whether the packaged IC is operating properly. After correctness, the packaged product can be shipped to the assembly plant to make the electronic product we have seen. Among the major semiconductor packaging and testing companies are Ampei, StarKing, J-devices, Unisem, Nepes, Riyueguang, Licheng, Nanmao, Shan State, KYEC, Fukhan, Lingsheng Precision, Xipin, Long electricity, excellent special. At this point, the semiconductor industry has completed the entire production task. Back blowing Bag Filter Anti - Blower Cloth Bag Dust Collector Anti - Blower Cloth Bag Dust Collector,High Efficiency Bag Filter,Cloth Bag Dust Collector,Anti-Blower Dust Collector Botou Youjian Environmental Protection Equipment Co. LTD. , http://www.btdustmachine.com
The back blowing bag filter condenses the advantages of all kinds of bag duster both at home and abroad. It is a new type of dust removal device which combines the mechanism of cyclone dust removal and filter dust removal mechanism, and uses special cleaning methods to remove dust.
Summary
The back blowing bag filter condenses the advantages of all kinds of bag duster both at home and abroad. It is a new type of dust removal device which combines the mechanism of cyclone dust removal and filter dust removal mechanism, and uses special cleaning methods to remove dust. The direct scour filter bag with high speed dust air flow is avoided and the service life of filter bag is prolonged; the clean air source of the back blowing dust source is introduced from the clean air flow after purification, which reduces the temperature difference between the air flow of the back blowing air and the Dust Collector and reduces the condensation phenomenon to the minimum limit.
Scope of application
The products are widely used in mine, metallurgy, machinery manufacturing, foundry, chemical, papermaking, refractory, cement, asbestos, industrial kiln and other industries, such as material recovery, flue gas dust control.
Working principle
After the dust air flow is cut into the dust collector, the large particle dust is separated and falling into the ash bucket first, and the small dust particles are suspended in the gas through the airflow distribution device, entering the filter chamber evenly, dispersing in the gap between the filter bags and being blocked by the filter bag, and the purification gas flow is discharged by the main fan.
Structure form of bag type dust collector
1. According to the shape of the bag, it can be divided into flat bags (trapezoidal and flat shaped) and round bags (cylindrical).
2. According to the way of entering and leaving the wind, it can be divided into: the downward wind and the upward wind, the wind and the direct current (only the plate-like flat bags).
3, according to the bag filter method is divided into: external filtration and internal filtration. The filter material consists of cotton fiber, wool fiber, synthetic fiber and glass fiber. The filter material made of different fibers has different properties. The commonly used filter material is 208 or 901 terylene flannelette, the use temperature is not more than 120 degrees C, the glass fiber filter bag after the silicone resin treatment, the temperature is generally not more than 250 degrees C, the cotton wool fabric is generally applicable to no corrosion; the temperature is below 80-90 centigrade gas.
Features of bag type dust collector
1, the dust removal efficiency is high, it can trap small particles with a diameter larger than 0.3 microns, and the efficiency of dust removal can reach more than 99%.
2, the use of flexible, handling air volume by hundreds of hours per hour in the room, small square meters of square meters near the machine tool to hundreds of thousands of cubic meters per hour, directly set up as a unit, also can be used as a large dusting room, that is, "bag house".
3, the structure of bag filter is relatively simple, stable operation, less initial investment (compared with ESP), easy maintenance. Therefore, the bag filter is widely used to eliminate dust pollution, improve the environment and recycle materials.
4. The key filter material of bag filter is now in service for more than 2 years, and has achieved 4-6 years' performance.
5. In dry and semi dry desulphurization systems, the role of SO2 in flue gas is further reduced.